ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.170
A 10GS/s 8-bit Current Steering DAC in 65nm CMOS Technology
Abstract— A 10GS/s 8-bit low power current steering DAC in TSMC 65nm CMOS technology is presented.
An ingenious way to minimize the mismatch is introduced by mirroring and shifting the current source cells.
Also, a switch driver which generates high-cross point and low-swing driving waveform is used in the DAC.
It increases the static and dynamic performance of the DAC. The converter adopts the segmented
thermometer decoder consisting 4MSBs and 4LSBs, trading off between the complexity and the power. The
spurious free dynamic range (SFDR) up to 43dB has been simulated over the entire Nyquist bandwidth at
10GS/s. The total power consumption is 37.5mW at 10GS/s. The DAC occupies an area of 0.7mm ×
Index Terms— CMOS, current source cells placement, switch driver, thermometer decoder.
Li Wenyuan, Song Chunyu
Institute of RF-&OE-ICs, Southeast University, CHINA
Cite: Li Wenyuan, Song Chunyu, "A 10GS/s 8-bit Current Steering DAC in 65nm CMOS Technology," Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering, pp. 983-987, Beijing, 25-27 June, 2017.