ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.169
An Enhanced Smart Card Memory Ciphering System Implementation on FPGA
Abstract— This paper describes about the design and implementation of an enhanced memory ciphering
system of a smart card prototype in Cyclone V System-on-a-Chip (SoC) 5CSEMA5F31C6N Field
Programmable Gate Array (FPGA) device. The comparison between the design implementation in this device
and in Xilinx’s Zynq-7000 XC7020-1-CLG484 FPGA device is explained in this paper in terms of resource
utilization and time requirements. The memory ciphering system in the smart card is capable to complete in
40ns that is a single cycle CPU of the smart card. The implementation in the Cyclone V SoC has the least
utilized logics and the highest maximum frequency (Fmax) that are 8,313 slices and 195 MHz respectively.
The smart card memory ciphering system provides significant enhancement in terms of security and
performance especially for smart card secured applications like national identification (ID), financial
transactions and health insurance.
Index Terms— Smart Card; AES; ARM Cortex A9; XC7Z020; XC4VLX60; 5CSEMA5F31C6N
Wira Firdaus Yaakob, Jahariah Sampe
Institute of Microengineering and Nanoelectronics, Universiti Kebangsaan Malaysia (UKM), Universiti Kebangsaan Malaysia. MALAYSIA
Cite: Wira Firdaus Yaakob, Jahariah Sampe, "An Enhanced Smart Card Memory Ciphering System Implementation on FPGA," Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering, pp. 977-982, Beijing, 25-27 June, 2017.