WCSE 2018 ISBN: 978-981-11-7861-0
DOI: 10.18178/wcse.2018.06.028

Narrowband Adjustable Time-Delay Line Design for Timed Array Antennas

Li Wenyuan, Dong Jinhua

Abstract— A 4GHz–4.5GHz narrowband adjustable time-delay line circuit is presented for timed array antennas. The proposed architecture consists of a coarse tuning section and a fine tuning section. The coarse tuning is composed of delay cells and switch and digital control parts. A seven-stage delay cell with an active-inductor load design is used to provide a considerable range tuning capability with low normalised delay variation over a wide frequency span, and the insertion loss is approximately −29dB at 4.25GHz. The LC artificial transmission line in fine tuning section can provide continuous delay. The circuit is implemented in a 180 nm CMOS process and occupies a small area of 1.06 mm2. The total relative delay can vary from 0ps to 200ps approximately, and the delay jitter is within 7%. The input return loss is better than -10dB, output return loss is better than -9dB. Under a supply voltage of 1.8V, the power consumption is only 46*1.8mW.

Index Terms— Passive, active, delay line, CMOS.

Li Wenyuan, Dong Jinhua
Institute of RF-&OE-ICs, Southeast University, CHINA


Cite: Li Wenyuan, Dong Jinhua, "Narrowband Adjustable Time-Delay Line Design for Timed Array Antennas," Proceedings of 2018 the 8th International Workshop on Computer Science and Engineering, pp. 156-160, Bangkok, 28-30 June, 2018.