Low-Power High-Speed 8-Bit Shift Register Using Double-Edge Triggered Flip-Flops
Abstract— This investigation presents an 8-bit shift register based on a lower-power double-edge triggered (DETFF) flip-flop. The 8-bit shift register based on the low-power DETFF is carried out by using Cadence Virtuoso version 5.1 and TSMC 0.18 μm CMOS technology. The major contribution of the proposed design is a method using a double-clocking technique to latch data bits such that shorter time delay and the less power dissipation are achieved at the same time. The all-PVT-corner (process, voltage, temperature) postlayout simulation results demonstrates 34.970 mW at the highest 125 MHz clock rate.
Index Terms— shift register, DETFF, low power, post-layout simulation, all-PVT.
National Sun Yat-Sen University, TAIWAN
Angger Baskoro, Onny Setyawati, Ponco Siwindarto
University of Brawijaya, INDONESIA
Cite: Angger Baskoro, Onny Setyawati, Ponco Siwindarto, Chua-Chin Wang, "Low-Power High-Speed 8-Bit Shift Register Using Double-Edge Triggered Flip-Flops," Proceedings of 2018 the 8th International Workshop on Computer Science and Engineering, pp. 151, Bangkok, 28-30 June, 2018.