WCSE 2017
ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.178

Efficient Reversible Arithmetic Logic Units Designs and Evaluation

Omkar S. Murkumbi, Tanmayee Tankasali, Nan Wang

Abstract— Every day, the brilliant minds of the semi-conductor industry thrive in bettering computing ICs. As a result of advances made by the silicon industry world, computing devices today process faster, occupy less area, and minimize overall power consumption. By Moore’s Law, the transistors on a die of silicon doubles in number every two years, which causes the leakage currents’ rates to increase rapidly. As of today, the feature size in transistor fabrication has reached 8 nm. In the coming years, the fabrication industry will approach to a saturation point in the feature size reduction. The electrical circuit’s energy consumption can be reduced if the operation performed is reversible in nature. This reversible computing opens up ways for quantum computing, which has been considered the best design approach for over five decades. In this paper, we will begin by discussing existing Arithmetic Logic Unit designs based on reversible structures. We then propose a new reversible gate named the OSG gate based on which two new ALU designs are presented. The designs and simulations were carried out on Xilinx ISE 13.2 design suite and the results are compared and evaluated.

Index Terms— ALU design, OSG gate, quantum switching, reversible gates

Omkar S. Murkumbi, Tanmayee Tankasali, Nan Wang
California State University, US

ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.17Xsrc="http://www.wcse.org/uploadfile/2019/0823/20190823055609629.png" style="width: 120px; height: 68px;" />[Download]

Cite: Omkar S. Murkumbi, Tanmayee Tankasali, Nan Wang, "Efficient Reversible Arithmetic Logic Units Designs and Evaluation," Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering, pp. 1028 -1032, Beijing, 25-27 June, 2017.