Design of Delay Cell and DLL Based on CMOS 65nm Process
Abstract— With the development of analog integrated circuits, the characteristics of signal timing have a
crucial impact on high-speed mixed-signal. Some delay cells can be designed to solve the delay differences
and also they have been widely used in Delay Locked Loop (DLL), equalizer, and phased antenna arrays
because it compensates the delay between the different signal paths. Moreover, the DLL's performance is
largely determined by the delay unit. Therefore, the research and design of delay unit has important value and
significance. The design and simulation are implemented by TSMC 65nm CMOS LP technology. DLL is
made up of the Voltage Control Delay Line (VCDL), XOR gate phase detector and Voltage-Current (V/I)
converter. The VCDL is implemented by cascading multi-level delay units, and the single delay unit uses
active-inductor peaking technology to achieve wideband low-latency performance. The chip consumes a
power of 31mW with 1.5V power and it occupies an area of 0.27mm2 which including I/O pads. The delay
time of designed single delay cell varies from 5.4ps to 7.1ps with 20% adjustment range within the
bandwidth of 1-7GHz, showed from the post-layout simulation results. The design of the delay cell and DLL
has some significance in the research of the low delay wide band delay circuit in the future.
Index Terms— DLL, Voltage Control Delay Line (VCDL), TSMC 65nm CMOS LP.
Wenyuan Li, Yan Zhang, Pusheng Liu, Feng Chen
Institute of RF-&OE-ICs, Southeast University, CHINA
Cite: Wenyuan Li, Yan Zhang, Pusheng Liu, Feng Chen, "Design of Delay Cell and DLL Based on CMOS 65nm Process," Proceedings of 2019 the 9th International Workshop on Computer Science and Engineering, pp. 829-833, Hong Kong, 15-17 June, 2019.