WCSE

A Dual-Mode on-Demand Page-Level Flash Translation Layer for Large Scale NAND Flash Memory

Abstract— With the rapid development of NAND flash technique and NAND-based solid-state devices (flash SSDs), whose capacity has doubled roughly every two years, the mapping table for page-level flash translation layers (FTLs) has become too large to be entirely stored in RAM in the engineering application. In this work, we have proposed a dual-mode on-demand page-level flash translation layer scheme (named DOPFTL hereafter), where extent mapping technology is adopted to compress mappings in a trace-adaptive way. Besides, two improvements are introduced to locate or update mappings for a read/update request with less overhead. One improvement is to add a field of cached translation page address (CTPA) in the global translation directory (GTD), which results in a benefit of time-saving in locating mappings. The other improvement is to append a new entry of LPN-PPN-LEN in compressed mode for updates, which results in a benefit of avoiding split or merge overhead. With these improvements, we have conducted extensive trace-driven evaluations of DOPFTL and compared it with the other start-of-the-art FTL schemes. Experimental results show that DOPFTL can achieve obvious improvement in cache hit rate than the conventional DFTL, which is a classical on-demand page-level FTL. Besides, DOPFTL can achieve an average cache hit rate of up to 0.89, close to that of TPFTL which is a demand-based page-level FTL with a translation page-level caching mechanism. Besides, DOPFTL can achieve obvious reduction in time overhead when compared with DFTL and TPFTL.

Index Terms—SSD, NAND Flash Memory, Flash Translation Layer (FTL), Address Translation, Mapping Cache

Jing Chen, Weijie Lin, Shiyue Cao, Zhiyuan Cheng
College of Information Science & Electronic Engineering, Provincial Key Laboratory of Micro-Nano Electronics and Smart System, Zhejiang University, CHINA

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Cite:Jing Chen, Weijie Lin, Shiyue Cao, Zhiyuan Cheng , " A Dual-Mode on-Demand Page-Level Flash Translation Layer for Large Scale NAND Flash Memory " Proceedings of 2020 the 10th International Workshop on Computer Science and Engineering (WCSE 2020), pp. 307-313, Shanghai, China, 19-21 June, 2020.