ISBN: 978-981-11-0008-6 DOI: 10.18178/wcse.2016.06.095
Design of Delay Locked Loop with Frequency Division Technique
Abstract— Design of delay locked loop (DLL) with frequency division technique is presented. The
proposed pseudo-differential delay cell increases the input clock frequency. To avoid the false locking or
harmonic locking problem, a simple start-control signal is added. The DLL design are implemented by IBM
0.13μm CMOS process. The static phase error of the DLL is 2.6ps at 3GHzand 8.5ps at 5GHz, respectively.
The peak-to-peak jitter values at 3GHz and 5GHz are 3.3ps and 1.7ps.The supply voltage is 1.2V.
Index Terms— delay locked loop, charge pump, phase frequency detector, delay cell, frequency division.
Wenyuan Li, Yurong Cao
Institute of RF-&OE-ICs, Southeast University, CHINA
Cite: Wenyuan Li, Yurong Cao, "Design of Delay Locked Loop with Frequency Division Technique," Proceedings of 2016 6th International Workshop on Computer Science and Engineering, pp. 563-566, Tokyo, 17-19 June, 2016.