WCSE 2017
ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.069

Implementation and Performance Evaluation of Pipelining Mechanism in 32-bit MIPS Architecture

Nan Wang, Ranjith Kumar, Rajath M. Basavaraj

Abstract— The demand for increasing the speed of instruction execution in processors and instruction accessing from memory leads to instruction level parallelism and the design of memory structures closer to the central processing unit. Such esteemed and efficient processors are built only after forming the base in the VLSI front end design stages. A microprocessor without Interlocked Pipeline Stages is a 32-bit RISC instruction set architecture. The principle used in MIPS design is to form pipeline stages such as fetch, decode, execute, memory access, and write back and make them work together efficiently in an overlapped way. The critical instruction types like Register type instructions, Load and Store instructions, and Branch instructions are taken into picture by considering the instruction set of a known processor. This paper aims at implementation and simulation of the 32-bit MIPS architecture as a RISC processor. The completed 32-bit MIPS architecture with pipelining mechanism is designed and simulated to produce outputs including execution time and propagation delays. The results are then analyzed and compared to show efficiency of the pipelining scheme by calculating CPIs with and without data dependency between the input instructions.

Index Terms— 32-bit MIPS design, pipelining, verilog HDL, RISC, CPI.

Nan Wang, Ranjith Kumar, Rajath M. Basavaraj
California State University, US


Cite: Nan Wang, Ranjith Kumar, Rajath M. Basavaraj, "Implementation and Performance Evaluation of Pipelining Mechanism in 32-bit MIPS Architecture," Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering, pp. 405-409, Beijing, 25-27 June, 2017.